1. Field of the Invention
The present invention relates to a Programmable Frequency Divider (PFD) and a frequency dividing method thereof, and more particularly, to a programmable frequency divider which is a core module of a frequency synthesizer using a Phase Locked Loop (PLL) for generating very high frequencies, and a frequency dividing method thereof.
2. Description of the Related Art
With the recent development of mobile communication environments, frequency synthesizers allowing standards, such as a Global System for Mobile communications (GSM), Global Positioning System (GPS), DCS 1800, Wideband Code-Division Multiple Access (WCDMA), and wireless LAN, etc., to stably operate at a high frequency clock ranging from 0.9 to 2.4 GHz have gained importance.
A frequency synthesizer generally includes a programmable divider (PD) for adjusting a divide ratio to divide a high-speed clock. Since such a programmable divider divides a high-speed clock generated by a voltage-controlled oscillator (generally called “VCO”), power consumption is very high. Accordingly, significantly reducing power consumption is very important in a frequency synthesizer design to meet the increasing requirements of the frequency synthesizer.
FIG. 1 shows the construction of an existing programmable frequency divider.
Referring to FIG. 1, the existing programmable frequency divider includes a dual modulus prescaler (DMP) having a divide ratio of N or (N+1), a program counter (PC) for counting clocks upto P, and a swallow counter (SC) for counting clocks upto S, wherein N is a basic divide ratio of the DMP, P is an input value of the PC, and S is an input value of the SC set from the outside (P>S).
If a high-speed clock Fin, from a VCO of a PLL is input to the DMP, the DMP divides the high-speed clock Fin by the divide ratio (N+1). The divided clocks Fin/(N+1) are applied simultaneously to both the PC and SC, and the PC and SC each counts the number of the divided clocks Fin/(N+1). Here, since P>S, the divided clocks Fin/(N+1) are first counted upto S by the SC, and then a modulus control signal (hereinafter, referred to as a MC signal) which is an output signal of the SC goes logic high (‘1’). In response to the MC signal which goes logic high, the DMP changes its divide ratio from (N+1) to N. The clocks Fin/N divided by the DMP are again input to the PC, the PC counts the number of the clocks Fin/N upto P, and when the count value reaches P, the PC generates a reset signal RST to reset the P and S values to ‘0’.
That is, the clock Fin is divided by the divide ratio (N+1) until the count value reaches S, and until the count value reaches P from when it reaches S, the clock Fin is divided at the divide ratio N. After the resetting, the counting and dividing operations described above are repeated.
A final divide ratio D of the clock Fin obtained by repeatedly performing the counting and dividing operations can be expressed by the following Equation.D=(n+1)*S+N*(P−S)=N*P+S 
In FIG. 1, Fout (that is, the output of the PD) are clocks obtained by dividing the Fin by the final divide ratio D.
However, the existing programmable divider has very high fan-out since the DMP supplies clocks divided by itself simultaneously to the two counters (that is, the SC and PC), as described above. Due to such very high fan-out, operation performance at high frequencies cannot be ensured and the two counters perform the same function unnecessarily (that is, the two counters perform counting in parallel), which significantly increases power consumption of the frequency synthesizer and also causes an increase of the chip area, resulting in a great increase of manufacturing costs.